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Home List of Titles Scalable optical packet switch architecture for low latency and high load computer communication networks
Please use this identifier to cite or link to this item: http://hdl.handle.net/1959.3/222084
- Scalable optical packet switch architecture for low latency and high load computer communication networks
- Calabretta, Nicola; Lucente, Stefano Di; Nazarathy, Yoni; Raz, Oded; Dorren, Harmen
- High performance computer and data-centers require PetaFlop/s processing speed and Petabyte storage capacity with thousands of low-latency short link interconnections between computers nodes. Switch matrices that operate transparently in the optical domain are a potential way to efficiently interconnect 1000's of inputs/outputs, complying the end-to-end latency (~1 μs) of these systems. Current rearrangeable non-blocking switches architectures (Benes, Omega, etc..) have a reconfiguration time (expressed in clock-cycles) at most of Mog2(N), N is the number of nodes. Assuming a clock cycle of 1 ns, it follows that the latency requirement cannot be met for N >; 100. Moreover, being the switch disable during this time, the packets are either lost or buffered, limiting the maximum load of the system. In this work we present a new strictly non-blocking switch architecture with a contention resolution sub system. Key point is that the new architecture supports highly distributed control that allows for reduction of the switching time to few nanoseconds regardless the N input/output nodes. Thus, the architecture can meet the latency requirement without limiting the load of the system.
- Publication type
- Conference paper
- Proceedings of the 13th International Conference on Transparent Optical Networks (ICTON 2011), Stockholm, Sweden, 26-30 June 2011 / Marek Jaworski and Marian Marciniak (eds.), pp. 1-4
- Publication year
- Clock-cycles; Computer architecture; Computer networks; Computers nodes; Contention resolution subsystem; Data centers; Distributed control; End-to-end latency; High load computer communication networks; High performance computer; In-band labels; Input-output nodes; Integrated optics; Label processor; Low-latency short link interconnections; Nonblocking switches architectures; Optical buffering; Optical interconnects; Optical packet switching; Optical signal processing; Optical switches; Packet switching; Petabyte storage capacity; Petaflop processing; Scalable optical packet switch architecture; Switching networks
- 9781457708800, 1457708809, 2161-2056 (series ISSN)
- Publisher URL
- Copyright © 2011 IEEE.
- Peer reviewed